With each passing week, it seems like more rumors are coming concerning AMD’s upcoming Zen processors. From previous reports, we had expected AMD to release Zen near the tail end of 2016 but revenue from the new CPUs was not expected till early 2017. According to the latest rumour though, AMD may have Zen out a bit earlier than expected, with an 8-core chip coming out as early as October, meaning there could be significant revenue from Black Friday and the holiday season.
An October launch pretty much falls smack dab in the middle of AMD’s late 2016/Q4 confirmed launch window. With an 8-core chip with potential SMT (Simultaneous Multi-Threading) for 16 threads, AMD is striking with a strong with a very competitive chip. Currently, Intel only has one consumer 8-core in the 5960X which is pretty pricey with a large TDP. An 8-core variant would also entice AMD users to consider an upgrade earlier as it doubles the thread count of current Piledriver CPUs on top of the 40%+ IPCincrease.
Launching under the Summit Ridge series, the 8-core also boasts a positively regular TDP at 95W. This considers favorably with what Intel has to offer, especially considering AMD is offering double the core count. This is probably due to toned down clock speeds, improved efficiency and the new 14nmLPP process, providing AMD with a jump of 3 process nodes. Intel, for instance, cut power by about 30%+ when they moved from 32nm to 14nm, at the while increasing performance.
Key to Zen, of course, will be how well it will perform. Based on AMD’s figures and what we have been able to glean from multiple leaks, Zen should hover around Haswell levels of IPC. The bigger question is how AMD prices Zen, though many will undoubtedly jump at the chance to buy a once again, IPC competitive AMD CPU. Hopefully, AMD’s expectations for Zen hold true. I for one, am finally hoping we will see 8C/16T CPUs enter the realm of mainstream hardware.
First off, Zen will introduce a new L0 cache, meaning that there will actually be 4 levels of cache. The L0 cache is a uOp cache, something Intel added back with Sandy Bridge. Paired with the uOp buffer, this will help reduce power consumption when running loops or if something needs to be re-executed quickly. Intel’s cache is 1.5KB so we can probably expect AMD to follow similarly as speed is more important than size.
Next up are changes to the L1 Instruction and Data caches. The L1 I$ will be 32KB, a drop compared to Steamroller/Excavator and K10 but back to the same size as Piledriver. The L1 D$ is also expected to be 32KB, a doubling over Steamroller and the same that of Excavator though still lower than K10. The reduced L1 I$ may be offset by the new uOp cache. The L2 may remain the same since the days of K10, with 512KB. This may be a problem if the rumoured inclusive cache design is used as 2304of the rumoured 8MB of L3 will be used in duplicating data. Having everything duplicated in L3 may make for better core-sharing and multi-threaded performance but limits everything to near L3 speeds for cache writes.
Overall, the cache changes suggest a move to ensure faster, rather than large caches. The increases to the caches also point to the focus on keeping the cores fed as well as high-speed cores with a long pipeline. This all helps with the 40%+ IPC improvement AMD is hoping for with Zen. Overall, Zen is looking to be a very wide and balanced design, borrowing from Intel and K10 but without any of the baggage of the past.
After many years of lagging CPU performance, AMD has suffered diminishing market and financial performance. This may change later this year as AMD comes back with their new Zen architecture that AMD originally expected to bring up to 40% IPC increase over their current lineup. According to AMD’s latest report, though, Zen may be performing better than their early estimates, with greater than 40% IPC increase over the current generation.
AMD has long been confident that Zen would deliver on its performance gains. After all, the new architecture is reported to bring instruction set parity with Intel and a reworked and more balanced design. In fact, rumours about a Zen Apple chip have surfaced, which if true, is a strong endorsement for AMD. Zen will also revamp the ageing 9xx series chipset and bring DDR4 and other new technologies with AM4.
While there is much to be optimistic, the biggest disappointment is that the rumour about an early 2016 release is wrong, with the originally suggested late 2016 launch being confirmed. This is despite the tape out having already been completed. The wording for the 40%+ IPC increase also suggests that the increase won’t be much greater than expected, otherwise, numbers like 45% or 50% would have been used. Hopefully, Zen will have what it takes to bring AMD back to the forefront and allow the company to continue with future releases and even stunning designs like this one.
TSMC has just scored a major CPU customer as AMD is allegedly moving their Zen CPUs over to the fab. Originally meant for GlobalFoundries 14nm process, delays at the once AMD owned fab have led to a change to use the 16nm process at TSMC, the same one used for AMD and Nvidia’s next-gen GPUs. Zen is AMD’s next CPU architecture, aimed at improving IPC by 40% over current Excavator products.
According to the source, GF has been facing issues with getting their 14nm production ramped up. The fab’s main owner, the government of Abu Dhabi, has been cutting expenses due to low oil prices. Due to that and difficulties in retooling the 28nm equipment to 14nm, volumes and yields on the new process are below expectations. It was also the delays for the 32nm process at GF that caused Bulldozer to launch later than expected back in 2011.
With both TSMC and GF offering FinFET processes, AMD should see good efficiency gains on top of moving to a new process. While AMD had previously been mum about which FinFET process it would use, most had expected GF to win out due to the long relationship between the two firms. With TSMC now confirmed, the biggest question is whether or not the fab can handle all the CPUs, GPUs and SoCs planned for next year. Hopefully, TSMC 16nmFF+ process will be able to hit the clocks speeds required of desktop CPUs.
Thank you WCCFTech for providing us with this information
AMD took a blow this past week after another major departure. While some have taken Jim Keller’s departure to be negative news, we aren’t so sure. Internally though, AMD still seems to be in high spirits and hopes are high for Zen.
Speaking for the Zen design team, engineer Suzanne Plummer is optimistic:
“It is the first time in a very long time that we engineers have been given the total freedom to build a processor from scratch and do the best we can do,” Plummer said. “It is a multi-year project with a really large team. It’s like a marathon effort with some sprints in the middle. The team is working very hard, but they can see the finish line. I guarantee that it will deliver a huge improvement in performance and (low) power consumption over the previous generation.”
Set on a 14nm FinFET process, Zen is expected to boost IPC by 40% over current Excavator designs. While that probably won’t be enough to catch up to Intel’s Skylake, it should place Zen withing striking distance of Ivy Bridge or Haswell. This would be good enough performance to claw back sales provided pricing is competitive. Zen is set to launch in Q4 2016.
Thank you myStatesman for providing us with this information
Despite launching the i7 6700K and i5 6600K based off the Skylake μArch earlier this month, Intel has kept the wraps on the μArch till IDF [Intel Developer Forum] 2015 today. We finally know what improvement and tweaks Intel has done to make Skylake a tad bit faster than Haswell.
While Intel extracted more efficiency and added more execution units to Haswell, most of the information released from IDF so far points to improving efficiency rather than increasing the brute force power of the chip. First of all, the front end received a number of improvements, with the Out-of-order Window increased to 224 from 192, the In-flight Stores from 42 to 56, Scheduler Entries grew to 97 from 60, the Allocation Queue from 56 to 64 and the Integer Register File from 168 to 180. All of these small improvements should help feed the cores better and improve efficiency, leading to lower power consumption and better IPC. Specific instructions like AES-GCM and AES-CBC also improved by 17% and 33% respectively.
Improvements were also made to other sections, with an improved ring bus, Last Level Cache and Hyper-Threading. These changes should help drive better multi-core efficiency, something that we’ve seen strong improvement in for multi-threaded tasks. This has been helped along with a better branch predictor, improved cache and buffer latency and bandwidth to feed the cores. Of course, the IMC is improved with support for DDR4 and the chipset is connected by the faster and wider DMI 3.0. As expected, power consumption also improved with better power gating of units in the cores, which should help reduce load temps if not all execution units are being used.
While Intel already has a very wide core with Haswell, with 8 execution ports, Skylake reportedly increases that number as well. No information about that has yet been released though we will probably get more information as Skylake specific presentations roll out through the rest of IDF 2015. We’ll bring you more information about Skylake as they come. It’s interesting though that despite all these improvements, IPC has only increased by a few percent over Haswell. You can find the full set of day 1 Skylake slides here.
While AMD has released some details about Zen at their Financial Analyst Day earlier this year, details have still been a bit scant. What we already know is that Zen will have a 40% IPC increase compared to Excavator, bringing AMD’s IPC much closer to Intel’s in one jump. Zen will also support a version of Simultaneous Multithreading (SMT) to support 2 logical processors per core. This will all be bundled on the AM4 platform with DDR4 support and use a FinFET process. Most critically, the CMT or cluster-based threading will be gone and each core will have 2 256bit FPUs and a good number of Integer ALUs.
Today though, we have a rumour that suggests that Zen will bring AMD to instruction set parity with Intel’s Haswell/Broadwell CPUs. With Excavator that launched earlier this year, AMD already caught up partially with AVX 2 which brings 256bit support to integer work, BMI2 and RDRAND for pseudo-random number generation. If Zen is to catch up to Haswell, it will probably add hardware acceleration support to CRC, SHA-256 and RSA algorithms and RDSEED for more pseudo-random number generation. interestingly, there is also suggestions that AMD’s SMT implementation will be compatible with the Intel’s meaning OS’s may not need to be patched, like they did with Bulldozer, to fully support the extra logical processor.
AMD may also support some of the new Skylake instructions like AVX 512 though we will have to wait and see. Part of this is due to the fact that Intel is yet to fully reveal what Skylake supports till IDF later this month. With Intel slipping in a refresh with Kaby Lake in 2016, AMD really has a good chance at a comeback if Zen performs well.
Thank you Fudzilla for providing us with the information
More Skylake details have leaked out ahead of its August launch and this time around, we’re being treated to what appears to be official Intel slides. Once again, it seems like Intel is emphasizing the iGPU side of things though we do see that Intel expects some decent IPC gains for the CPU.
According to Intel, Skylake will bring IPC improvements of 10% to single threaded operations and 20% to multithreaded tasks. The single-threaded performance increase does seem to fall in the range we’ve seen from some leaked benchmarks which have put IPC improvements at about 8-11%. 10% is probably closer to a best case scenario all things being equal. The 20% on the multithreaded side of things also matches up with what we known, with leaked benchmarks showing strong improvements in multi-threaded efficiency and Hyper-Threading.
Real benefits from 14nm also show for the mobile side of things, with the increased power efficiency allowing much better CPU and iGPU performance for the low power Y SKUs. Intel is claiming about 30% improvement in battery life, which given that the CPU and iGPU only contribute a portion, is pretty amazing. A lot of value added features like better touch, audio, video and camera features are also being included. Overall, it looks like Intel is selling Skylake as an incremental improvement for desktops users but brings much more to mobile users.
Thank you FanlessTech for providing us with this information
New information for AMD’s upcoming CPU architecture has been leaked ahead of the company’s annual Financial Analyst Day. The leak image appears to be an official slide details the block diagram for the next generation architecture. If this slide is legitimate, this will offer the first glimpse into the innards of AMDs first major desktop architecture change since Bulldozer was introduced in 2011.
On the left side, the diagram shows a complete Excavator module, looking very much the same from a high level as the Bulldozer before it. You can see the two integer clusters and the single shared floating point cluster. One such cluster makes up two cores and it’s due to the shared nature as well as the small integer clusters that AMD single thread performance has been suffering. AMD gambled on increased parallelism to counter the weaker integer units and GPU compute to address floating point performance. However, computing parallelism has been elusive as many tasks are sequential in nature and GPU computing is still only for some specific workloads. The failure of the gambit has seen AMD processor performance stagnate over the past few years.
This new Zen core appears to a complete change in AMD’s strategy. On the right side, we can see what appears to be one Zen core. In a move that hearkens back to the old K8/10 and Intel’s Core architecture, this single core is given much more resources to play with. With a total of 6 integer pipelines and 2 -256bit AVX floating point units (with potential to combine for 512bit instructions), the core has much more resources to play with, something that should lead to a significant improvement in IPC and single threaded performance. This is the same number of interger and floating point units found in K10, though obviously with improvements.
Many commentators had previously suggested that AMD should have evolved K10 with is much better IPC rather than pursue Bulldozer. While working off K10 would have ben complicated, taking design cues from K10 as Zen likely did, was probably the best way forward to improving performance. This information builds on previous information pointing to DRR4, HBM and quad channel support coming in 2016. Intel will be launching their own mainstream DDR4 Skylake processor later this year. Perhaps, Intel will finally have some high-end competition in 2016, though then again, we will have to wait and see.