Class Action Lawsuit Launched Against AMD Over Bulldozer Core Count

AMD is set to face legal action over claims that it falsely advertised one of its previous generation CPU architectures. The Bulldozer CPU had a mixed response when released, due in part to its unique design which hampered the chip’s competition against Intel’s equivalent processor. Now, according to Legal Wire, AMD is set for a belated kicking over the Bulldozer architecture after a class-action lawsuit was filed in the U.S. District Court for the Northern District of California.

The lawsuit alleges that AMD falsely advertised its Bulldozer CPUs as having eight cores, despite the chip being unable to handle eight instructions simultaneously, and thus is guilty of false advertising, fraud, breach of express warrant, negligent misrepresentation and unjust enrichment under the Consumer Legal Remedies Act of California’s Unfair Competition Law.

The trouble stems from the Bulldozer’s “Clustered Integer Core” micro-architecture, which combines two integer cores with a one floating-point core and a shared L2 cache, with multiple modules combined to form the CPU. But, according to Tony Dickey who filed the suit, the two integer cores cannot operate independently, which leaves the chips only able to operate four simultaneous commands, not eight.

Dickey claims that “tens of thousands of consumers” that do not understand the complexity of CPUs have been fooled into buying chips that cannot operate in the same manner as a “true eight-core” processor would, causing “material performance degradation”.

Image courtesy of Softpedia.

AMD Patch Reveals Highly Competitive Zen Architecture Details

All hopes at AMD are pinned on their new Zen CPU architecture performing well against Intel’s currently superior lineup. While we have seen some leaked block diagrams and claims of 40% IPC improvement come out, other details have been scant. We now have a patch that details pretty much what Zen will look like, at least at the block level. Zen is also expected to bring instruction set parity between the two x86 CPU players.

Overall, Zen may have a total of 10 executions ports. These are meant to feed the integer side 4 ALUs and 2 AGUs, and the FPU consisting of 2 128it FMAC, each with 2 128BIT add and 2 128bit mul. There is a chance that AMD will have fewer execution ports as the ALUs may share ports with the FPU. In order to get the most out of the architecture though, having more execution ports is crucial. With such a wide core, AMD will really let their SMT (Hyper-Threading) stretch its legs with mixed workloads.

Compared to Bulldozer, the ALU count remains the same but being in the same core should give a massive boost to single-threaded performance. Zen does lose out 2 AGUs in the process, but that shouldn’t hurt it too much given our experience with K10. The fact they should be AVX2 compatible should also mean improvements on throughput, at least if the software uses the latest extensions. For the FPU, Zen basically doubles the throughput, which goes a long way towards boosting IPC in floating point heavy workloads. It’s interesting that Zen goes with 128bit units but we’re expecting them to combine to do AVX instructions which should provide parity with Haswell/Skylake. Furthermore, by allowing the FPU to split into 2 128bit units, older instructions may actually run better than on Intel which still can only process 1 128bit instruction despite the execution units 256bit width.

On the instruction decode side of things, Zen cuts things down from Steamroller/Excavator, with only 4 instructions per clock compared to 8. Zen ‘s decoders won’t need to feed 2 cores however as in the Bulldozer design, meaning the real decode rate is the same provided you are running more than 1 core at a time. 4 instructions per clock is also where Intel is currently sitting. For the cache, it looks like we will be seeing a return to the Cat (Jaguar) and K10 design, with 512Kb of L2 per core and 32KB of L1 data, with 32kb of L1 instruction likely as well. While it is a drop, Zen won’t have to feed as many cores and with less cache thrashing it should actually perform better.

With Zen, it really looks like AMD has taken a lot of lessons from K10, Jaguar, Bulldozer and even Intel to create what appears to be a really strong CPU architecture on paper. By combining all of the strong traits from previous and current CPUs, AMD may finally give Intel a run for their money. It’s just too bad we’ll have a year to wait before Zen will arrive. Given Intel’s pace though, Zen should still be plenty competitive in a years time.

Thank you dresdenboy for providing us with this information

Intel Skylake μArch Analysis from IDF 2015

Despite launching the i7 6700K and i5 6600K based off the Skylake μArch earlier this month, Intel has kept the wraps on the μArch till IDF [Intel Developer Forum] 2015 today. We finally know what improvement and tweaks Intel has done to make Skylake a tad bit faster than Haswell.

While Intel extracted more efficiency and added more execution units to Haswell, most of the information released from IDF so far points to improving efficiency rather than increasing the brute force power of the chip. First of all, the front end received a number of improvements, with the Out-of-order Window increased to 224 from 192, the In-flight Stores from 42 to 56, Scheduler Entries grew to 97 from 60, the Allocation Queue from 56 to 64 and the Integer Register File from 168 to 180. All of these small improvements should help feed the cores better and improve efficiency, leading to lower power consumption and better IPC. Specific instructions like AES-GCM and AES-CBC also improved by 17% and 33% respectively.

Improvements were also made to other sections, with an improved ring bus, Last Level Cache and Hyper-Threading. These changes should help drive better multi-core efficiency, something that we’ve seen strong improvement in for multi-threaded tasks. This has been helped along with a better branch predictor, improved cache and buffer latency and bandwidth to feed the cores. Of course, the IMC is improved with support for DDR4 and the chipset is connected by the faster and wider DMI 3.0. As expected, power consumption also improved with better power gating of units in the cores, which should help reduce load temps if not all execution units are being used.

While Intel already has a very wide core with Haswell, with 8 execution ports, Skylake reportedly increases that number as well. No information about that has yet been released though we will probably get more information as Skylake specific presentations roll out through the rest of IDF 2015. We’ll bring you more information about Skylake as they come. It’s interesting though that despite all these improvements, IPC has only increased by a few percent over Haswell. You can find the full set of day 1 Skylake slides here.

Intel Unlocked Skylake Launch Date Revealed

Hardwareluxx is reporting that Intel will be releasing its first Skylake processors sometime between August 6th and 9th. Intel is timing the release of the i7-6700K and i5-6600K to be in line with Gamescom which also falls on the previously mentioned dates. As unlocked processors, both the 6700K and the 6600K will likely be targeted towards gamers and overclockers, making the Gamescom timing understanding. Other Skylake chips will launch later in August.

Both chips will be the first of Intel’s 14nm chips based on the new Skylake architecture. Skylake will move the VRM off the CPU package and back on to the motherboard, likely reducing the heat given off the CPU package and improving overclockability. DDR4 will also be standard but DDR3L may also be supported. That will be dependent on the new LGA 1151 motherboards and Z170 chipset for unlocked chips. Other notable additions are the new AVX512 instructions, Thunderbolt 3, 20 PCIE 3.0 lanes and L4 eDRAM cache.

The chips run at 3.5/3.9Ghz and 4.0/4.2Ghz for the i5 and i7 respectively. While a bit slower than the current Devil’s Canyon chips, the L4 eDRAM and other architecture improvements should boost performance overall. At 95W, the new chips are suggested to have a 9% IPC gain from leaked benchmarks. As we near this rumoured launch date, more information is likely to be released so stay tuned!

Thank you HardwareLUXX for providing us with this information

Russia Debuts Homegrown x86 Compatible CPU

In pursuit of independence from American chip makers Intel and AMD, Russia has started selling computers equipped with the Elbrus-4C. Also known as the Elbrus-4S, the chip was announced just about a year ago and started production in late 2014. It’s made by MCST, also known as the Moscow Center for SPARC Technologies. The processor is meant to scale from normal everyday tasks all the way to server and high-performance computing needs.

In the processor industry, x86 patents are a rarity as the major holders, Intel and AMD jealously guard them. In order to be x86 compatible, Elbrus translates the x86 program code into its own machine code via a virtual machine. It’s own internal architecture is known as Elbrus and is based off VLIW (Very Long Instruction Word). While uncommon for CPUs to use, VLIW designs are used by Intel’s Itanium lineup and AMD used VLIW designs prior to their move to GCN.

Not surprisingly, Elbrus-4C has a long way to catch up to AMD, let alone Intel. The chip is being made on TSMC’s 65nm process, which Intel and AMD moved away from in 2007 and 2008 respectively. Clock rates are somewhat slow as well at 800mhz peak. Performance while not amazing is able to trade blows against Intel’s Atom D510, a low power mobile chip from 2010. With the lofty goal of technological independence and security from the West though, Russia might be willing accept being behind the curve. Combined with China’s Longsoon development, these designs may not be the best but might be good enough.

AMD Challenges Intel with Zen Cores Featuring 40% IPC Boost

While AMD’s Financial Analyst Day has not quite yielded the announcements we were hoping for, a critical new CPU architecture has been confirmed. Called Zen, this new CPU architecture will debut in 2016’s high-end FX platform.

Featuring Simultaneous Multithreading (SMT) for the first time Zen will be a much more flexible platform. AMD is also suggesting that up to 40% IPC (Instructions per Clock) gain over Excavator. If that IPC gain be fully realized, that would put Zen at about Sandy/Ivy Bridge levels of IPC, making AMD quite competitive again in the CPU space if clock speeds are decent.

Other improvements include the use of FinFETs, a design process that involves the use of 3D transistors, something that will lead to improved power efficiency. The core has also been revamped to feature improved cache system, a major issue that was present in the Bulldozer series of chips. DDR4 compatibility will also be introduced granting improved memory bandwidth. This makes a lot of sense as the AM4 platform will be shared with the 2016 APUs as well.

A major downer though not unexpected is that the 2016 APUs may not run Zen cores just yet. This may be an issue as this will create a mismatch between the APU and CPU side of things. AMD has previously kept the APU side of things behind the CPU side, but only debuted Steamroller in APUs. AMD has been vague about the APU side so far so maybe the Zen cores might sneak in though that is unlikely.

While it’s great that AMD is finally planning a comeback in the CPU arena, Zen will have to compete against Intel’s Cannon Lake CPU family in 2016. So while AMD may have made a big jump in performance, their target is a moving one. AMD may well catch up as Skylake and Cannon Lake aren’t expected to be high IPC boosters and Intel’s 10nm might be delayed. One year from now, there may well again be competition for desktops CPUs again.

Full AMD CPU Roadmap Leaks

AMD is either orchestrating a hype campaign or they really can’t keep their secrets. This time around, the CPU roadmaps for both desktop and mobility have been leaked out to 2016. These roadmaps clarify a number of rumors and leaks over the past while as well lay out AMD’s long-term strategy.

For the desktop segment, 2015 is pretty much more of the same. Piledriver continues to drive the performance segment on AM3+ while Puma cores hold the low end. Kaveri gets a rebrand to “Godavari” making previous rumors around Godavari moot.

An important confirmation is the use of 14nm throughout the product stack. 14nm will bring AMD to parity with Intel Skylake. While Intel is set for 10nm in 2016, there have been signs that there will delays with that process. 14nm also means continued usage of Global Foundries, maybe with Samsung as a secondary supplier since the designs can now be easily be ported between the two firms.

Zen looks to be AMD’s go to architecture for 2016, covering everything from the performance to low power segments. It’s ability to replace the low-end Puma cores likely means the architecture is well power optimized and efficient. Scaling from 2-8 cores, some rumours are also pointing to simultaneous-multithreaded making an appearance, meaning up to 16 active threads are possible. It does look like rumours of a true 16 core consumer CPU were wrong though. The top end chip is codenamed Summit Ridge while the mainstream APUs are Bristol Ridge, complete with HSA 1.0. The small form factor and budget range will be served by Basilisk. Both Summit Ridge and Bristol Ridge are on the new FM3 socket while Basilisk is BGA.

On the mobile side of things, it much of the same. In 2015 Carrizo gets an update to Excavator cores, likely a minor tweak of the current Steamroller. For 2016, Bristol Ridge serves the performance and mainstream segments at 15-35W while Basilisk targets low power at 5-15W. Ultra low power moves from Amur with ARM A57 cores to Styx which sports up to 2 K12 cores to hit about 2W.

With all this information out already, it looks like May 6th will an important day not just for AMD fans but for PC fans in general. I doubt there will be much left to leak on the CPU side from AMD until then. 2016 looks like it will be a very interesting year if AMD can finally start competing with Intel using Zen.

More AMD Zen Slides Leak Ahead of Financial Analyst Day

AMD has been leaking slides like a sieve before their 2015 Financial Analyst Day. This latest slide sheds even more light on how the Zen cores, detailed earlier, will all fit together to form a CPU. With some rumours pointing to as many as 16 cores, a 4 core unit is more interesting as it’s unlikely that most users will want that many cores, even if they can get their hands on them. There is a little hint that suggests there will be units greater than 4 cores as the slide mentions that “multiple units can be combined for even greater performance”. Whether that means up to 16 cores remains to be seen.

As expected, the cores share a large pool of L3 cache. At 8MB, that’s pretty much expected for a quad core unit as AMD currently uses that much in their 4M/8C CPUs and even Intel hovers about 6-8MB for their quad cores as well. In terms of L2 cache, the same old size since K10 of 512KB per core remains. Most intriguing is that Zen moves to an inclusive cache design. While AMD has already dropped the exclusive cache found in K7/8/10, even Bulldozer kept some level of cache exclusive. More mundane is the mention of a high-speed interconnect to tie all the cores together.

While this new slide doesn’t share a lot of new information, it does shed new light on Zen the clarify some important points. May 6th may prove a very important day for both AMD and the PC industry as a whole.