One of the first applications that came to mind with HBM was pairing it up with an AMD APU. Proven to work as VRAM with the Fiji GPUs last year, HBM also has possible applications to act as a high-speed cache for other applications where density is important. While we’ve known that AMD has been planning APUs with HBM, the latest report points to Raven Ridge, the 2017 series of APUs that follow Bristol Ridge, to have HBM.
According to the source, Raven Ridge will utilize AMD’s upcoming Zen CPU cores likely paired with Polaris GCN iGPU. With 14nmLPP and Polaris, AMD can stuff a much larger iGPU with their APUs without worrying too much about extra costs or ballooning die size. However, even with the current generation of APUs, the iGPU is bottlenecked at the high-end, something even DDR4 won’t fully solve.
In order to keep growing APU GPU performance, AMD also needs to increase the memory bandwidth. One way, of course, is to use eDRAM as Intel has done with notable success. That, however, is expensive, leading to the top SKUs costing near $400. In comes HBM to the rescue at a relatively lower cost, allowing a large yet budget friendly cache pool to help reduce bandwidth constraints. To produce this, AMD has tapped Amkor, the same firm that worked on Fiji interposers to package Raven Ridge.
With at least, 1GB HBM buffer, the APU will be very well fed, allowing for the iGPU to grow to at least R7 370 performance levels before running out of steam. AMD is also probably working on HMC to supplant HBM in the future as well. If AMD manages to pull this off, Raven Ridge will be the most potent APUs yet, securing the crown against Intel.
First off, Zen will introduce a new L0 cache, meaning that there will actually be 4 levels of cache. The L0 cache is a uOp cache, something Intel added back with Sandy Bridge. Paired with the uOp buffer, this will help reduce power consumption when running loops or if something needs to be re-executed quickly. Intel’s cache is 1.5KB so we can probably expect AMD to follow similarly as speed is more important than size.
Next up are changes to the L1 Instruction and Data caches. The L1 I$ will be 32KB, a drop compared to Steamroller/Excavator and K10 but back to the same size as Piledriver. The L1 D$ is also expected to be 32KB, a doubling over Steamroller and the same that of Excavator though still lower than K10. The reduced L1 I$ may be offset by the new uOp cache. The L2 may remain the same since the days of K10, with 512KB. This may be a problem if the rumoured inclusive cache design is used as 2304of the rumoured 8MB of L3 will be used in duplicating data. Having everything duplicated in L3 may make for better core-sharing and multi-threaded performance but limits everything to near L3 speeds for cache writes.
Overall, the cache changes suggest a move to ensure faster, rather than large caches. The increases to the caches also point to the focus on keeping the cores fed as well as high-speed cores with a long pipeline. This all helps with the 40%+ IPC improvement AMD is hoping for with Zen. Overall, Zen is looking to be a very wide and balanced design, borrowing from Intel and K10 but without any of the baggage of the past.
With Zen set to arrive within the year, AMD is starting to get software ready for their revolutionary CPU architecture. According to a new Linux patch, AMD not only has Zen planned for this year but also a previously rumoured but never confirmed Zepplin CPU. Most interestingly is the connection between Zepplin and Zen which takes 3 letters from Zepplin, suggesting that they may be released, just as Piledriver and Vishera were also related for AMD.
According to the patch, Zepplin is part of the AMD’s Family 17h series of chips. This follows the previous 15h Bulldozer and its derivatives and the stellar K8(8h) and K10(10h). The 17h family is also expected to be the one Zen belongs too, with the K12 being the ARM-based lineup coming soon as well.
On Zen, the patch reveals some new information about how the LLC or Last Level Cache, usually the L3. Each Core Complex or Core Cluster of 8 threads shares 1 LLC unit. Given the use of SMT, we can expect Zen to be based on clusters of 4 cores. This is quite expected as larger CPUs use interconnects to link various different clusters of cores and their LLC together in order to function as a larger core. While Intel’s implementation carries a low penalty for accessing the LLC of another cluster in the chip, AMD’s L3 has been less robust so Zen will hopefully remedy this. You can see Intel’s Xeon E7 v3 design below with clusters formed by 2 cores and linked through buffered switches and interconnects.
Finally, Zen is also expected to feature up to 32 physical cores possible with 64 threads in total. This suggests that the massive Zen CPUs rumoured may actually come to fruition. This should allow AMD to take back some of that lucrative data centre and supercomputing market. All that remains is for Zen to finally deliver and bring AMD back into the black.
Ever since Llano launched back in 2011, AMD has been pushing their APUs as being the next big thing. Combining a powerful CPU and GPU on one die, the APU allows even budget users to enjoy strong graphics to play games or use it for compute. In 2016, AMD is looking to combine their new Zen CPU architecture with their Polaris based graphics and it looks like something revolutionary will happen. According to a leaked paper, AMD may be planning a multi-core Zen APU coupled with a massive iGPU and an HBM cache with 128GB/s of bandwidth
For AMD, APUs have stayed strong even as their CPU line faltered, with their iGPU beating out Intel solutions. This changed though with Intel’s Iris Pro graphics that came with an eDRAM cache, with the high-speed cache helping put Intel neck and neck with AMD’s top APUs. The only bright side for AMD is that Intel’s chips have cost significantly more than AMD’s offerings. With the launch of a competitive CPU architecture in Zen, a new GPU architecture in Polaris and a large HBM cache, AMD has a chance to surge past Intel in this critical segment.
At a peak of 128GB/s, the HBM cache performs similarly to that of the memory of graphics cards like the GTX 760 and 960. If AMD adds in a high-performance iGPU, the APU has the chance to match or even exceed $150 graphics cards. With this APU, AMD is truly bringing gaming to the masses. Maybe in 2016, we may finally see AMD APUs powering Apple products.
When Intel frist revealed that the eDRAM cache introduced with Iris Pro could be accessed by the CPU, many users were elated. CPU performance had long been relatively stagnant and extra faster cache would help improve performance. With up to 50GB/s in each direction, the relatively massive 128MB eDRAM L4 cache would bridge the gap between the large yet slow DDR3/4 and the small yet fast L3 cache. Unfortunately though, Intel has no plans to introduce this to socketed Skylake chips, limiting it to soldered BGA SKUs.
One reason many had hoped that Intel would introduce socketed Skylake with eDRAM was due to Broadwell. With the socketed i7 5775C and i5 5675C, Intel paired LGA 1150 Broadwell with 128MB of eDRAM as L4. What’s more, both chips were also unlocked and overclockable. Many had hoped that the unlocked Skylake SKUs or even a locked SKU would offer the same combination. Even with the lackluster overclocks, the 5775C can actually match overclocked 6700K in performance. This means a Skylake part with eDRAM would likely far surpass our current 6700K.
There is still room for Intel to add eDRAM to a socketed chip later on with the Kaby Lake refresh. Set for 2016, that will be little more than a minor refresh on the Skylake architecture and probably a drop in replacement on LGA 1151 motherboards. Even then though, we may not truly see eDRAM as a real option till AMD pressures Intel with Zen combined with maybe HBM or eDRAM.
Thank you TechReport for providing us with this information
A good toolbox for your storage drive is something that’s worth just as much as the drive itself and Crucial has just released an upgrade to their software, the Storage Executive tool.
The new version is 3.20 and it now features Momentum Cache, an intelligent caching feature that can enhance the drives burst performance by up to ten times. The caching software uses your idle system memory to cache redundant writes and in return it also helps to increase the overall lifetime of your storage drive. Only the writes that need to go to the drive are actually written and frequent read data is stored in your memory for quick access.
Anyone owning a Crucial SSD can take advantage of this, but the ones that made the switch to DDR4 more than the rest. We’ve recently seen what DDR4 is capable off, with memory running around 4GHz. That speed will be equally returned when used as RAM disk or caching area.
In addition to the new features, Storage Executive also allows users to update the drives to the latest firmware, monitor the drive’s temperature and health, reset the drive’s encryption password, and easily check how much storage has been used.
“We want everyone to enjoy the benefits of solid state storage,” said Jonathan Weech, storage marketing manager, Crucial. “Software that optimises performance and keeps Crucial SSDs running efficiently is another example of how we make upgrading easy.”
Intel has launched the brand new Braswell SoCs that will take the place of the current Bay Trail-D SoCs. The four new SoCs are built on the same 14nm process as Broadwell CPUs, with two dual-core and two quad-core models.
The two new dual-core Braswell parts that are in the Celeron line, the N3000 and the N3050. They both have GPUs with a base frequency of 320MHz and boost to 600MHz and 1MB of L2 cache. The Celeron N3000 has a base clock of 1.04GHz and boosts to 2.08GHz. The N3050 is clocked higher with a base clock of 1.60GHz and a boost of 2.16GHz.
The quad-core Braswell parts both have 2MB of L2 cache with a 640MHz GPU that will boost to 700MHz. The Celeron N3150 comes in with a base clock of 1.6GHz and boosts up to 2.08GHz. The Pentium N3700 has the same base of 1.6GHz but boosts higher, up to 2.4GHz.
All Braswell SoCs support up to DDR3-1600 memory and have a TDP of 6W, all except the N3000 which comes in with a TDP of 4W.
Seagate introduced us to the concept of Kinetic Open Storage Platform back in 2013 for the first time, and now they’re presenting the first HDD for this system. The Seagate Kinetic 4TB hard drive is designed for cloud storage applications and has built-in ethernet abilities.
The object-based storage drive has a built-in operating system and direct ethernet connectivity thereby eliminating bottlenecks in software applications by direct connection as well as reducing the total cost of ownership by eliminating the need for legacy software and hardware.
Besides the built-in operating system, the Seagate Kinetic hard drive has 512MB RAM and 64MB cache as well as dual SGMII Ethernet 1Gb/s ports and of course an application processor. Seagate says this system can bring down the overall running costs as much as 50% for data-centres by eliminating the need for extra hardware and the power consumption that comes with that.
The Kinetic Open Storage Platform is backed by a lot of large providers such as AOL, HP, Digital Sense and many more. A really interesting concept that Seagate cooked up and one that incredible useful for our ever-growing need for storage. Live demonstrations took place this week at the OpenStack Summit in Paris.
Thanks to Seagate for providing us with this information
Have you heard of GeoCaching? I had never heard about it, until a couple of days ago. It is kind of like a treasure hunt for the outdoors that require us to use different technologies that many of us carry with us every day. Our cell phones, though there is other cool equipment that we could use to aid us in our hunts.
GeoCaching is an interesting game that can be really simple or just the opposite, extremely difficult. Typically a GeoCache is a small waterproof container that has a logbook where other GeoCachers write their name and the date they found the cache. Some caches contain objects in the container, which the finder is able to trade for something of equal value. Once the person is done signing and trading, they replace the container where they found it, and move onto the next cache.
A cache could be as small as a bag containing a single piece of paper for a log, or larger such as an ammunition box, which could contain trinkets (generally of low value).
Everyone is welcome to join in on the fun of GeoCaching, which can be a ton of fun. If you decide to try it out, be aware of your surroundings. Be courteous of those who setup the cache, this is intended to be a fun game for all to play.
Things you might want to bring with you, a pencil or pen to sign the log, small trinkets for trade, a gps device (such as a cell phone), a good pair of shoes, a walking stick, yourself. The more difficult the cache the more tools you might want to bring with you, such as a rope, working gloves, etc.